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Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Overview
The LU3X34FT is a fully integrated 4-port 10/100 Mbits/s physical layer device with transceiver. This part was designed specifically for 10/100 Mbits/s switches. These applications typically require stringent functionality in addition to very tight board space, power, and cost requirements. The LU3X34FT supports MII interface. The LU3X34FT was designed to conform fully with all pertinent specifications, from the ISO/IEC 11801 and EIA/TIA 568 cabling guidelines to ANSI X3.263 TP-PMD to IEEE* 802.3 Ethernet specifications.
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Built-in 10 Mbits/s transmit filter 10 Mbits/s PLL exceeding tolerances for both preamble and data jitter 100 Mbits/s PLL, combined with the digital adaptive equalizer, robustly handles variations in risefall time, excessive attenuation due to channel loss, duty-cycle distortion, crosstalk, and baseline wander Transmit rise-fall time manipulated to provide lower emissions, amplitude fully compatible for proper interoperability Programmable scrambler seed for better FCC compliancy
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Features
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IEEE 802.3u Clause 28 compliant autonegotiation for full 10 Mbits/s and 100 Mbits/s control
Extended management support with interrupt capabilities PHY MIB support Low-power, 480 mA max Low-cost, 160 PQFP packaging
4-port, single-chip integrated physical layer and transceivers for 10Base-T, 100Base-TX, or 100Base-FX functions
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IEEE 802.3 compatible 10Base-T and 100Base-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver
Interface support for MII Autonegotiation pin configurability on a per-port basis Combined TX, 10Base-T, FX drivers, receivers, and signal detect circuit Built-in, analog 10 Mbits/s receive filter, removing the need for external filters
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* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
Table of Contents
Contents Page
Overview................................................................................................................................................................... 1 Features ................................................................................................................................................................... 1 Description................................................................................................................................................................ 4 Pin Information ......................................................................................................................................................... 5 Pin Descriptions........................................................................................................................................................ 6 Functional Description ............................................................................................................................................ 11 Media Independent Interface (MII) ...................................................................................................................... 11 100Base-X Module.............................................................................................................................................. 12 10Base-T Module ................................................................................................................................................ 17 Clock Synthesizer................................................................................................................................................ 19 Autonegotiation ................................................................................................................................................... 19 Reset Operation .................................................................................................................................................. 20 MII Registers .......................................................................................................................................................... 23 dc and ac Specifications......................................................................................................................................... 36 Absolute Maximum Ratings................................................................................................................................. 36 Clock Timing........................................................................................................................................................... 37 Package Properties ................................................................................................................................................ 47
Tables
Page
Table 1. Twisted-Pair Magnetic Interface ................................................................................................................. 6 Table 2. Twisted-Pair Transceiver Control/Transmitter Control ................................................................................. 6 Table 3. MII Interface ............................................................................................................................................... 6 Table 4. Autonegotiation/LED Configuration ............................................................................................................ 8 Table 5. Special Mode Configurations ..................................................................................................................... 9 Table 6. Clock and Chip Reset ................................................................................................................................ 9 Table 7. Power and Ground ................................................................................................................................... 10 Table 8. Symbol Coding Table ............................................................................................................................... 14 Table 9. Initial Values for Autonegotiation Registers .............................................................................................. 22 Table 10. MII Management Registers .................................................................................................................... 23 Table 11. Control Register (Register 0h) ............................................................................................................... 23 Table 12. Status Register Bit Definitions (Register 1h).......................................................................................... 25 Table 13. PHY Identifier (Register 2h) ................................................................................................................... 27 Table 14. PHY Identifier (Register 3h) ................................................................................................................... 27 Table 15. Advertisement (Register 4h) .................................................................................................................. 27 Table 16. Autonegotiation Link Partner Ability (Register 5h) ................................................................................. 28 Table 17. Autonegotiation Expansion Register (Register 6h) ................................................................................ 28 Table 18. Programmable LED (Register 11h) Only Under PHY Address for Port 2............................................... 29 Table 19. False Carrier Counter (Register 13h) ..................................................................................................... 30 Table 20. Receive Error Counter (Register 15h).................................................................................................... 31 Table 21. PHY Control/Status Register (Register 17h).......................................................................................... 31 Table 22. Config 100 Register (Register 18h)........................................................................................................ 32 Table 23. PHY Address Register (Register 19h) ................................................................................................... 33 Table 24. Config 10 Register (Register 1Ah) ......................................................................................................... 34 Table 25. Status 100 Register (Register 1Bh) ....................................................................................................... 34 Table 26. Status 10 Register (Register 1Ch) ......................................................................................................... 34 Table 27. Interrupt Mask Register (Register 1Dh) ................................................................................................. 35 Table 28. Interrupt Status Register (Register 1Eh) ................................................................................................ 35 Table 29. Absolute Maximum Ratings ................................................................................................................... 36 Table 30. Operating Conditions ............................................................................................................................. 36 2 Lucent Technologies Inc.
Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Table of Contents (continued)
Tables (continued) Page
Table 31. dc Characteristics................................................................................................................................... 36 Table 32. Clock Timing .......................................................................................................................................... 37 Table 33. Transmit Clock (Input and Output).......................................................................................................... 38 Table 34. Management Clock ................................................................................................................................ 39 Table 35. MII Receive Timing ................................................................................................................................ 40 Table 36. MII Transmit Timing ................................................................................................................................ 41 Table 37. Transmit Timing ...................................................................................................................................... 42 Table 38. Receive Timing ...................................................................................................................................... 43 Table 39. Reset and Configuration Timing............................................................................................................. 44 Table 40. PMD Characteristics .............................................................................................................................. 45
Figures
Page
Figure 1. Block Diagram .......................................................................................................................................... 4 Figure 2. Pin Diagram.............................................................................................................................................. 5 Figure 3. 100Base-X Data Path............................................................................................................................. 13 Figure 4. 10Base-T Module Data Path .................................................................................................................. 18 Figure 5. Hardware RESET Configurations........................................................................................................... 21 Figure 6. Clock Timing........................................................................................................................................... 37 Figure 7. Transmit Clock (Input and Output).......................................................................................................... 38 Figure 8. Management Clock ................................................................................................................................ 39 Figure 9. MII Receive Timing................................................................................................................................. 40 Figure 10. MII Transmit Timing .............................................................................................................................. 41 Figure 11. Transmit Timing .................................................................................................................................... 42 Figure 12. Receive Timing..................................................................................................................................... 43 Figure 13. Reset and Configuration Timing........................................................................................................... 44 Figure 14. PMD Characteristics............................................................................................................................. 45 Figure 15. Connection Diagrams (10/100Base-TX Operation).............................................................................. 46
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
Description
MII INTRZ P3 P2 P1 P0
GLOBAL INTERRUPT 10BASE-T PCS REF_CLK 10M/100M CLOCK RECOVERY CLOCK SYNTHESIS 100BASE-X PCS LED'S PORTS[3:0]
LED OUTPUTS
MANAGEMENT CONTROL
MDIO MDC
SQUELCH/SIG_ DETECT, BLW CORRECTION, ADAPTIVE EQ.
AUTONEG/ LINK 10/100 TRANSMIT REGISTERS CONFIGURATION
RX
TX
5-7907(F).r2
Figure 1. Block Diagram
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Lucent Technologies Inc.
Pin Information
10FD_0 RXVDD0 RX+_0 RX-_0 RXGND0 REF100_0 TX+_0 TX-_0 TXVDD0 TXVDD1 TX-_1 TX+_1 REF100_1 RXGND1 RX-_1 RX+_1 RXVDD1 REFGND CSVDD10 CSGND10 CSGND100 CSVDD100 REF10 RXVDD2 RX+_2 RX-_2 RXGND2 REF100_2 TX+_2 TX-_2 TXVDD2 TXVDD3 TX-_3 TX+_3 REF100_3 RXGND3 RX-_3 RX+_3 RXVDD3 10FD_3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Advance Data Sheet June 1999
Lucent Technologies Inc.
LU3X34FT 160 PQFP 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 ER RSTZ TESTMSEL FOSEL_1/LEDLNK_1 100HD_1/LEDACT_1 10HD_1/SD-_1/LEDFD_1 ANEN_1/SD+_1/LED100_1 LEDVDD1 LEDGND1 FOSEL_0/LEDLNK_0 100HD_0/LEDACT_0 10HD_0/SD-_0/LEDFD_0 ANEN_0/SD+_0/LED100_0 CLK_25 TXEN_0 TXD_0[0] TXD_0[1] TXD_0[2] TXD_0[3] TXER_0 IOVDD1 IOGND1 TXCLK_0 SUBGND1 CRS_0/SERSEL COL_0/100FD_0 RXDV_0 RXD_0[0] HSVDD1 HSGND1 TMVDD1 RXD_0[1] RXD_0[2] RXD_0[3] RXER_0 RXCLK_0 IOVDD2 IOGND2 1OFD_1 1OFD_2 TXCLK_1 TXEN_1 TXD_1[0] TXD_1[1] TXD_1[2] TXD_1[3] IO_VDD3 IO_GND3 TXER_1 CRS_1/PHY_AD[2] COL_1/100FD_1 RXDV_1 RXD_1[0] DIGVDD1 DIGGND1 RXD_1[1] RXD_1[2] RXD_1[3] RXER_1 RXCLK_1 IOVDD4 IOGND4 RXCLK_2 RXER_2 RXD_2[3] DIGVDD2 DIGGND2 RXD_2[2] RXD_2[1] RXD_2[0] RXDV_2 COL_2/100FD_2 CRS_2/PHY_AD[3] TXER_2 TXD_2[3] TXD_2[2] TXD_2[1] TXD_2[0] TXEN_2 TXCLK_2
Figure 2. Pin Diagram
INTZ PAUSE TPTXTR ISOLATE ANEN_2/SD+_2/LED100_2 10HD_2/SD-_2/LEDFD_2 100HD_2/LEDACT_2 FOSEL_2/LEDLNK_2 LEDGND2 LEDVDD2 ANEN_3/SD+_3/LED100_3 10HD_3/SD-_3LEDFD_3 100HD_3/LEDACT_3 FOSEL_3/LEDLNK_3 TXEN_3 TXD_3[0] TXD_3[1] TXD_3[2] TXD_3[3] TXER_3 COL_3/100FD_3 CRS_3/PHY_AD[4] MDC MDIO SUBGND2 HSVDD2 HSGND2 TMGND1 IOGND6 TXCLK_3 IOVDD6 RXDV_3 RXD_3[0] RXD_3[1] RXD_3[2] RXD_3[3] RXER_3 RXCLK_3 IOGND5 IOVDD5
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
5-7908(F).r3
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
Pin Descriptions
Table 1. Twisted-Pair Magnetic Interface Pin No. 7, 12, 29, 34 8, 11, 30, 33 Pin Name TX+_[0:3] TX-_[0:3] I/O O Pin Description Transmit Driver Pairs. These pins are used to send 100Base-T MLT-3 signals across category 5 UTP , 10Base-T Manchester signals across category 3/5 UTP cable in twisted-pair operation, or PECL data in fiber mode. Receive Pair. These pins receive 100Base-T MLT-3 data, 10Base-T Manchester data from the UTP cable in twisted-pair mode, or PECL data in fiber mode.
3, 16, 25, 38 4, 15, 26, 37
RX+_[0:3] RX-_[0:3]
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Table 2. Twisted-Pair Transceiver Control/Transmitter Control Pin No. 6, 13, 28, 35 23 160 Pin Name REF100[0:3] REF10 ER I/O I I I Pin Description Reference Pin for 100 Mbits/s Twisted-Pair Driver. The value of the connected resistor is TBD . Reference Pin for 10 Mbits/s Twisted-Pair Driver. The value for the connected resistor is TBD . Transmit Driver Edge Rate Control. When set to 1, the rise time of the transmit data will be less than TBD ns. This pin is latched at powerup and reset. Network Interface Tri-State Control. When high, the transmit drivers for all four ports are tri-stated.
43
TPTXTR
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Table 3. MII Interface Pin No. 1, 122, 121, 40 Pin Name 10FD[0:3] I/O I Pin Description 10 Mbits/s Full-duplex Capability Configuration Input. It is latched into bit 6 of register 04h (autonegotiation ability register) at reset. It is also used to configure a port to 10 Mbits/s full-duplex mode if autonegotiation is disabled. Each of these pins has an internal 40 k pull-up. 100 Mbits/s Full-duplex Capability Configuration Input. During reset, it is latched into bit 8 of register 04h (autonegotiation ability register) at reset. It is also used to configure a port to 100 Mbits/s fullduplex mode if autonegotiation is disabled. Each of these pins has an internal 40 k pull-up. After reset: In half-duplex mode, these pins are an output indicating collision status. MII Transmit Clock For Ports 0 Through 2. Its frequency is 2.5 MHz in 100 Mbit mode, 25 MHz in 10 Mbit nibble mode, and 10 MHz in 10 Mbit serial mode. Transmit Enable. Ports 0 through 3.
135, 110, 89, 61
COL_[0:3]/ 100FD_[0:3]
I/O
138, 120, 81, 70
TXCLK_[0:3]
O
146, 119, 82, 55
TXEN_[0:3]
I
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Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Pin Descriptions (continued)
Table 3. MII Interface (continued) Pin No. 142, 143, 144, 145 115, 116, 117, 118 86, 85, 84, 83 59, 58, 57, 56 141, 112, 87, 60 127, 128, 129, 133 103, 104, 105, 108 96, 93, 92, 91 76, 75, 74, 73 102, 97, 77, 126 62 Pin Name TXD_0[3:0] TXD_1[3:0] TXD_2[3:0] TXD_3[3:0] TXER_[0:3] RXD_0[3:0] RXD_1[3:0] RXD_2[3:0] RXD_3[3:0] RXER_[0:3] CRS_3/ PHY_AD[4] I/O I I I I I O O O O O I/O Pin Description MII Transmit Data for Port 0. MII Transmit Data for Port 1. MII Transmit Data for Port 2. MII Transmit Data for Port 3. Transmit Error Signal for Each Port. MII Receive Data for Port 0. MII Receive Data for Port 1. MII Receive Data for Port 2. MII Receive Data for Port 3 in Switch Mode. Receive Error Condition for Ports 0--3. PHY Address 4. During reset, this pin is input pin for PHY_ADDRESS[4] configuration. This pin has an internal 40 k pull-down. CRS Output. After reset, this is the CRS output for port 3. It is asserted only during receive activity. PHY Address 3. During reset, this is an input pin for PHY_ADDRESS[3] configuration. This pin has an internal 40 k pull-down. CRS Output. After reset, this is the CRS output for port 2. It is asserted only during receive activity. PHY Address 2. During reset, this is an input pin for PHY_ADDRESS[2] configuration. This pin has an internal 40 k pull-down. CRS Output. After reset, this is the CRS output for port 1. It is asserted only during receive activity. Serial Select. During reset, this is an input pin, serial select for 10 Mbits/s mode. This pin has an internal 40 k pull-down. CRS Output. After reset, this is the CRS output for port 0. It is asserted only during receive activity. Receive Data Valid Signal for Ports 0--3. Receive Clock Output for Ports 0--3. Its frequency is 25 MHz in 100 Mbit mode, 2.5 MHz in 10 Mbit nibble mode, and 10 MHz in 10 Mbit serial mode. Management Data Port. An external resistive pullup is needed on this pin. Management Clock. Max clock rate is 2.5 MHz.
88
CRS_2/ PHY_AD[3]
I/O
111
CRS_1/ PHY_AD[2]
I/O
136
CRS_0/ SERSEL
I/O
134, 109, 90, 72 125, 101, 98, 78 64 63
RXDV_[0:3] RXCLK_[0:3]
O O
MDIO MDC
I/O I
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
Pin Descriptions (continued)
Table 4. Autonegotiation/LED Configuration Pin No. 148, 154, 45, 51 Pin Name ANEN_[0:3] LED100_[0:3] SD+_[0:3] I/O I/O Pin Description Autonegotiation Enable. During reset, if the FOSEL pin detects logic low during reset, these are input pins to configure ports 0--3 to enable autonegotiation and sets bit 12 in register 0. Each of these pins has an internal 40 k pull-up. Speed LED Output. After reset and in twisted-pair mode, these are LED outputs indicating 100 Mbits/s line speed for ports 0--3. Signal Detect Input. After reset and in fiber mode, these pins are signal detect + inputs. 10 Mbits/s Half-duplex. During reset, these are 10 Mbits/s half-duplex configuration inputs for ports 0--3. The logic level of this pin is latched into bit 5 of register 4 at reset. If autonegotiation is disabled, this pin also affects the initial speed and duplex registers of register 0. Each of these pins has an internal 40 k pull-up. LED Full-Duplex Status. After reset and in twistedpair mode, these are the LED outputs indicating fullduplex status for ports 0--3. Signal Detect Input. After reset and in fiber mode, these pins are the signal detect input from the fiber transceiver. 100 Mbit Half-duplex. 100 Mbit half-duplex configuration inputs for ports 0--3. During reset, the logic level of this pin is latched into bit 7 of register 4 at reset. If autonegotiation is disabled, this pin also affects the initial speed and duplex registers of register 0. Each of these pins has an internal 40 k pullup. LED Activity. After reset and in twisted-pair mode, these are the LED outputs indicating transmit or receive activity for ports 0--3. Signal Detect Input. After reset and in fiber mode, these pins are the signal detect input from the fiber transceiver. FOSEL. These are input pins to configure ports 0--3 into fiber-optic mode. Each of these pins has an internal 40 k pull-down. LED Link Status. After reset, these are the LED outputs indicating link status for ports 0--3.
149, 155, 46, 52
10HD_[0:3] LEDFD_[0:3] SD-_[0:3]
I/O
150, 156, 47, 53
100HD_[0:3] LEDACT_[0:3]
I/O
151, 157, 48, 54
FOSEL [0:3] LEDLNK_[0:3]
I/O
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Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Pin Descriptions (continued)
Table 5. Special Mode Configurations Pin No. 42 Pin Name PAUSE I/O I Pin Description Pause. During reset: Logic level of this pin is latched into register 4, bit 10 of all four ports. It is used for informing the autonegotiation link partner that the MAC sublayer has pause/ flow control capability of operation when set in fullduplex mode. This must not be set to 1 unless FD is also set. A weak resistive pull-up/pull-down is required to program this function. Open-Drain Output. This pin has open-drain output. Its active-low output indicates interrupt condition. Test Mode Select. To allow parallel access to this register. Users should connect it to low. 1 = test mode. 0 = normal operation. Isolate. This is an input pin that controls MII isolate mode. In isolate mode, all MII inputs are ignored and MII outputs are tri-stated.
41 158
INTZ TESTMSEL
I/O I
44
ISOLATE
I
Table 6. Clock and Chip Reset Pin No. 147 159 Pin Name CLK_25 RSTZ I/O I I Pin Description 25 MHz Reference Clock Input. Reset. A hardware reset is accomplished by applying a negative pulse, with a duration of at least 1 ms.
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
Pin Descriptions (continued)
Table 7. Power and Ground Plane RX Analog VCC Pin Name RXVDD0 RXVDD1 RXVDD2 RXVDD3 TXVDD0 TXVDD1 TXVDD2 TXVDD3 CSVDD10 CSVDD100 DIGVDD1 DIGVDD2 TMVDD IOVDD1 IOVDD2 IOVDD3 IOVDD4 IOVDD5 IOVDD6 HSVDD1 HSVDD2 LEDVDD1 LEDVDD2 Pin No. 2 17 24 39 9 10 31 32 19 22 107 95 130 140 124 114 100 80 71 132 66 153 50 Associated Ground Pin Name RXGND0 RXGND1 RXGND2 RXGND3 REFGND -- Pin No. 5 14 27 36 18 --
TX Analog
CS Digital
CSGND10 CSGND100 DIGGND1 DIGGND2 TMGND1 IOGND1 IOGND2 IOGND3 IOGND4 IOGND5 IOGND6 HSGND1 HSGND2 LEDGND1 LEDGND2 SUBGND1 SUBGND2
20 21 106 94 68 139 123 113 99 79 69 131 67 152 49 137 65
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Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
size data path, RXDV signals the presence of data on RXD, RXER indicates the validity of data, and RXCLK carries the receive clock. Depending upon the operation mode, RXCLK signal is generated by the clock recovery module of either the 100Base-X or 10Base-T receiver. Status Interface. Two status signals, COL and CRS, are generated in each of the four channels to indicate collision status and carrier sense status to the MAC. COL is asserted asynchronously whenever the respective channel of LU3X34FT is transmitting and receiving at the same time in a half-duplex operation mode. CRS is asserted asynchronously whenever there is activity on either the transmitter or the receiver. In full-duplex mode, CRS is asserted only when there is activity on the receiver. Operation Modes Each channel of the LU3X34FT supports three operation modes and an isolate mode as described below. 100 Mbits/s Mode. For 100 Mbits/s operation, the MII operates in nibble mode with a clock rate of 25 MHz. In normal operation, the MII data at RXD[3:0] and TXD[3:0] are 4 bits wide. In bypass mode (either BYP_4B5B or BYP_ALIGN option selected), the MII data takes the form of 5-bit code-groups. The least significant 4 bits appear on TXD[3:0] and RXD[3:0] as usual, and the most significant bits (TXD[4] and RXD[4]) appear on the TXER and RXER pins, respectively. 10 Mbits/s Nibble Mode. For 10 Mbits/s nibble mode operation, the TXCLK and RXCLK operate at 2.5 MHz. The data paths are 4 bits wide using TXD[3:0] and RXD[3:0] signal lines. 10 Mbits/s Serial Mode. This mode is selected by strapping the SERSEL pin (pin 136) to logic high level during powerup or reset. When operating in this mode, the LU3X34FT accepts NRZ serial data on the TXD[0] input and provides NRZ serial data output on RXD[0] with a clock rate of 10 MHz. The unused MII inputs and outputs (TXD[3:1] and RXD[3:1]) are ignored during serial mode. The PCS control signals, CRS and COL, continue to function normally. RXDV, RXER, and TXER signals are also ignored. MII Isolate Mode. The LU3X34FT implements an MII isolate mode that is controlled by bit 10 of each one of the four control registers (register 0h). At reset, LU3X34FT will initialize this bit to the logic level of the ISOLATE pin (pin 44). After reset, content of this register follows the logic level of the ISOLATE pin. Setting the bit to a 1 will also put the port in MII isolate mode. 11
Functional Description
The LU3X34FT integrates four 100Base-X physical sublayer (PHY), 100Base-TX physical medium dependent (PMD) transceiver, and four complete 10Base-T modules into a single-chip for both 10 Mbits/s and 100 Mbits/s Ethernet operation. It also supports 100Base-FX operation through external fiber-optic transceivers. This device provides an IEEE 802.3u compliant media independent interface (MII) to communicate between the physical signaling and the medium access control (MAC) layers for both 100Base-X and 10Base-T operations. The device is capable of operating in either full-duplex mode or half-duplex mode in either 10 Mbits/s or 100 Mbits/s operation. Operational modes can be selected by hardware configuration pins, software settings of management registers, or determined by the on-chip autonegotiation logic. The 10Base-T section of the device consists of the 10 Mbits/s transceiver module with filters and a Manchester ENDEC module. The 100Base-X section of the device implements the following functional blocks:
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100Base-X physical coding sublayer (PCS) 100Base-X physical medium attachment (PMA) Twisted-pair transceiver (PMD)
The 100Base-X and 10Base-T sections share the following functional blocks:
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Clock synthesizer module (CSM) MII registers
IEEE 802.3u autonegotiation
Each of these functional blocks is described below.
Media Independent Interface (MII)
The LU3X34FT implements IEEE 802.3u Clause 22 compliant MII interface as described below. Interface Signals Transmit Data Interfaces. Each MII transmit data interface comprises seven signals: TXD[3:0] are the nibble size data path, TXEN signals the presence of data on TXD, TXER indicates substitution of data with the HALT symbol, and TXCLK carries the transmit clock that synchronizes all the transmit signals. TXCLK is supplied by the on-chip clock synthesizer. Receive Data Interfaces. Each receive data interface also comprises seven signals: RXD[3:0] are the nibble Lucent Technologies Inc.
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
LU3X34FT requires a single initialization sequence of 32 bits of preamble following powerup/hardware reset. This requirement is generally met by the mandatory pull-up resistor on MDIO or the management access made to determine whether preamble suppression is supported. While the LU3X34FT will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required as specified in IEEE 802.3u. The PHY device address for LU3X34FT is stored in the PHY address register (register address 19h). Upper 3 bits of the PHY address are initialized by the three I/O pins designated as PHY_AD[4:2] during powerup or hardware reset and can be changed afterward by writing into register address 19h. The lower 2 bits of the PHY address are initialized to the port number of the PHY during powerup or hardware reset. MDIO Interrupt. The LU3X34FT implements interrupt capability that can be used to notify the management station of certain events. Interrupt requested by any of the four PHYs is combined in this pin. It generates an active-low interrupt on the INTZ output pin whenever one of the interrupt status registers (register address 1Eh) becomes set while its corresponding interrupt mask register (register address 1Dh) is unmasked. Reading the interrupt status register (register 1Eh) shows the source of the interrupt and clears the interrupt output signal. In addition to the INTZ pin, the LU3X34FT can also support the interrupt scheme used by the TI ThunderLAN MAC. This option can be enabled by setting bit 11 of register 17h. Whenever this bit is set, the interrupt is signaled through the INTZ pin and embedded in the MDIO signal.
Functional Description (continued)
When in isolate mode, the specified port on the LU3X34FT does not respond to packet data present at TXD[3:0], TXEN, and TXER inputs and presents a high impedance on the TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS outputs. The LU3X34FT will continue to respond to all management transactions while the PHY is in isolate mode. Serial Management Interface The serial management interface (SMI) is used to both obtain status from and to configure the PHY. This mechanism corresponds to the MII specifications for 100Base-X (Clause 22), and supports registers 0 through 6. Additional vendor-specific registers are implemented within the range of 16 to 31. All the registers are described in the register section. Management Register Access. The SMI consists of two pins, management data clock (MDC) and management data input/output (MDIO). The LU3X34FT is designed to support an MDC frequency ranging up to the IEEE specification of 2.5 MHz. The MDIO line is bidirectional and may be shared by up to 32 devices. The MDIO pin requires a pull-up resistor which, during IDLE and turnaround periods, will pull MDIO to a logic one state. Each MII management data frame is 64 bits long. The first 32 bits are preamble consisting of 32 contiguous logic one bits on MDIO and 32 corresponding cycles on MDC. Following preamble is the start-offrame field indicated by a <01> pattern. The next field signals the operation code (OP): <10> indicates READ from MII management register operation, and <01> indicates WRITE to MII management register operation. The next two fields are PHY device address and MII management register address. Both of them are 5 bits wide and the most significant bit is transferred first. During READ operation, a 2-bit turnaround (TA) time spacing between register address field and data field is provided for the MDIO to avoid contention. Following the turnaround time, a 16-bit data stream is read from or written into the MII management registers of the LU3X34FT. The LU3X34FT supports a preamble suppression mode as indicated by a 1 in bit 6 of the basic mode status register (BMSR, address 01h). If the station management entity (i.e., MAC or other management controller) determines that all PHYs in the system support preamble suppression by reading a 1 in this bit, then the station management entity need not generate preamble for each management transaction. The 12
100Base-X Module
The LU3X34FT implements 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as illustrated in Figure 3. Bypass options for each of the major functional blocks within the 100Base-X PCS provides flexibility for various applications. 100 Mbits/s PHY loopback is included for diagnostic purposes.
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Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description (continued)
RXCLK CLOCK RECOVERY
FORX FOSD
DESCRAMBLER
RXD[3:0]
4B/5B DECODE
EQUALIZER
SERIAL-TO PARALLEL
TPRX
BYP_4B5B BYP_ALIGN CRS RXDV RXEN RECEIVE STATE
BYP_ SCR 100M PHY LOOPBACK PATH
100BASE-X RECEIVER
COL TXCLK TXEN TXER
100BASE-X TRANSMITTER TRANSMIT STATE
BYP_ALIGN BYP_4B5B BYP_SCR PARALLEL-TO-SERIAL MLT-3 STATE MACHINE 10/100 TRANSMIT
TPTX
TXD[3:0]
4B/5B ENCODE
SCRAMBLER
PECL DRIVER
FOTX
5-7909(F).r1
Figure 3. 100Base-X Data Path
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
Following onset of the TXEN signal, the 4B/5B symbol encoder replaces the first two nibbles of the preamble from the MAC frame with a /J/K code-group pair (11000 10001) start-of-stream delimiter (SSD). The symbol encoder then replaces subsequent 4B codes with corresponding 5B symbols. Following negation of the TXEN signal, the encoder substitutes the first two IDLE symbols with a /T/R code-group pair (01101 00111) end-of-stream delimiter (ESD) then continuously injects IDLE symbols into the transmit data stream until the next transmit packet is detected. Assertion of the TXER input while the TXEN input is also asserted will cause the LU3X34FT to substitute HALT code-groups for the 5B code derived from data present at TXD[3:0]. However, the SSD (/J/K) and ESD (/T/R) will not be substituted with HALT code-groups. As a result, the assertion of TXER while TXEN is asserted will result in a frame properly encapsulated with the /J/K and /T/R delimiters which contains HALT code-groups in place of the data code-groups. The 100 Mbit symbol decoder translates all invalid code-groups into 0Eh by default. In case the ACCEPT HALT register is set (bit 5 of register 18h), the HALT code-group (00100) is translated into 05h instead.
Functional Description (continued)
100Base-X Transmitter The 100Base-X transmitter consists of functional blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a 125 Mbits/s serial data stream. This data stream may be routed either to the on-chip twisted-pair PMD for 100Base-TX signaling, or to an external fiber-optic PMD for 100Base-FX applications. The LU3X34FT implements the 100Base-X transmit state machine as specified in the IEEE 802.3u standard, Clause 24 and comprises the following functional blocks in its data path:
s s s
Symbol encoder Scrambler block Parallel/Serial converter and NRZ/NRZI encoder block
Symbol Encoder. The symbol encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) symbols for transmission. This conversion is required to allow control symbols to be combined with data symbols. Refer to the table below for 4B to 5B symbol mapping. Table 8. Symbol Coding Table Symbol Name 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R 14 5B Code [4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 4B Code [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined
Interpretation Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F IDLE: interstream fill code First start-of-stream delimiter Second start-of-stream delimiter First end-of-stream delimiter Second end-of-stream delimiter Lucent Technologies Inc.
Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description (continued)
Table 8. Symbol Coding Table (continued) Symbol Name H V V V V V V V V V V 5B Code [4:0] 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 4B Code [3:0] undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined HALT: transfer error Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code and receiver become active simultaneously. Collision detection is indicated by the COL pin of the MII. For full-duplex applications, the COL signal is never asserted. A collision test register exists at address 0, bit 7. When this bit is high, COL is asserted if TXEN is high. 100Base-X Receiver The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbits/s receive data stream. The LU3X34FT implements the 100Base-X receive state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbits/s receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application. Alternatively, the receive data stream may be generated by an external optical receiver as in a 100Base-FX application. The receiver block consists of the following functional blocks:
s s
Interpretation
Scrambler Block. For 100Base-TX applications, the scrambler is required to control the radiated emissions at the media connector and on the twisted-pair cable. The LU3X34FT implements a data scrambler as defined by the TP-PMD stream cipher function. The scrambler uses an 11-bit ciphering linear feedback shift register (LFSR) with the following recursive linear function: X[n] = X[n - 11] + X[n - 9] (modulo 2) The output of the LFSR is combined with data from the encoder via an exclusive-OR logic function. By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. A seed value for the scrambler function can be loaded by setting bit 4 of register 18h. When this bit is set, the content of bits 10 through 0 of register 19h that compose the 5-bit PHY address and a 6-bit user seed, will be loaded into the LFSR. By specifying unique seed value for each PHY in a system, the total EMI energy produced by a repeater type application can be reduced. Parallel to Serial and NRZ-NRZI Conversion. After the transmit data stream is scrambled, data is loaded into a shift register and clocked out with a 125 MHz clock into a serial bit stream. The serialized data is further converted from NRZ to NRZI format, which produces a transition on every Logic 1 and no transition on Logic 0. Collision Detect. During 100 Mbits/s half-duplex operation, collision condition is detected if the transmitter Lucent Technologies Inc.
Clock recovery module NRZI/NRZ and serial/parallel decoder Descrambler Symbol alignment block Symbol decoder Collision detect block Carrier sense block Stream decoder block
s s s s s s
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
into 4B nibbles. The symbol decoder first detects the /J/K symbol pair preceded by IDLE symbols and replaces the symbol with MAC preamble. All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R symbol pair denoting the end-of-stream delimiter (ESD). The translated data is presented on the RXD[3:0] signal lines with RXD[0] represents the least significant bit of the translated nibble. Valid Data Signal. The data valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV is asserted when the first nibble of translated /J/K is ready for transfer over the media independent interface (MII). It remains active until either the /T/R delimiter is recognized, link test indicates failure, or no signal is detected. On any of these conditions, RXDV is deasserted. Receiver Errors. The RXER signal is used to communicate receiver error conditions. While the receiver is in a state of holding RXDV asserted, the RXER will be asserted for each code word that does not map to a valid code-group. 100Base-X Link Monitor The 100Base-X link monitor function allows the receiver to ensure that reliable data is being received. Without reliable data reception, the link monitor will HALT both transmit and receive operations until such time that a valid link is detected. The LU3X34FT performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10 Mbits/s link status to form the reportable link status bit in serial management register 1, and driven to the LEDLNK pins. When persistent signal energy is detected on the network, the logic moves into a link-ready state after approximately 500 s, and waits for an enable from the autonegotiation module. When received, the link-up state is entered, and the transmit and receive logic blocks become active. Should autonegotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. Carrier Sense. Carrier sense (CRS) for 100 Mbits/s operation is asserted upon the detection of two noncontiguous zeros occurring within any 10-bit boundary of the receive data stream.
Functional Description (continued)
Clock Recovery. The clock recovery module accepts 125 Mbits/s scrambled NRZI data stream from either the on-chip 100Base-TX receiver or from an external 100Base-FX transceiver. The LU3X34FT uses an onboard digital phase-locked loop (PLL) to extract clock information of the incoming NRZI data, which is then used to retime the data stream and set data boundaries. After power-on or reset, the PLL locks to a free-running 25 MHz clock derived from the external clock source. When initial lock is achieved, the PLL switches to lock to the data stream, extracts a 125 MHz clock from the data and use it for bit framing of the recovered data. NRZI/NRZ and Serial/Parallel Conversion The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B codegroup's boundary. Data Descrambling. The descrambler acquires synchronization with the data stream by recognizing IDLE bursts of 40 or more bits and locking its deciphering linear feedback shift register (LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, the incoming data is XORed by the deciphering LFSR and descrambled. In order to maintain synchronization, the descrambler continuously monitors the validity of the unscrambled data that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler, the hold timer starts a 722 s countdown. Upon detection of sufficient IDLE symbols within the 722 s period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the link state monitor does not recognize sufficient unscrambled IDLE symbols within the 722 s period, the descrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. Register 18h, bit 3, can be used to extend the timer to 2 ms. Symbol Alignment. The symbol alignment circuit in the LU3X34FT determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the descrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. Symbol Decoding. The symbol decoder functions as a look-up table that translates incoming 5B symbols 16
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
far end fault, all receive and transmit MII activity is disabled/ignored. 100Base-TX Transceiver LU3X34FT implements a TP-PMD compliant transceiver for 100Base-TX operation. The differential transmit driver is shared by the 10Base-T and 100Base-TX subsystems. This arrangement results in one device that uses the same external magnetics for both the 10Base-T and the 100Base-TX transmission with simple RC component connections. The individually waveshaped 10Base-T and 100Base-TX transmit signals are multiplexed in the transmit output driver section. Transmit Drivers. The LU3X34FT 100Base-TX transmit driver implements MLT-3 translation and waveshaping functions. The rise/fall time of the output signal is closely controlled to conform to the target range specified in the ANSI TP-PMD standard. Twisted-Pair Receiver. For 100Base-TX operation, the incoming signal is detected by the on-chip twistedpair receiver that comprises the differential line receiver, an adaptive equalizer and baseline wander compensation circuits. The LU3X34FT uses an adaptive equalizer which changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable.
Functional Description (continued)
The carrier sense function is independent of symbol alignment. CRS is asserted during either packet transmission or reception. When the IDLE symbol pair is detected in the receive data stream, CRS is deasserted. CRS is intended to encapsulate RXDV. Bad SSD Detection A bad start-of-stream delimiter (bad SSD) is an error condition that occurs in the 100Base-X receiver if carrier is detected (CRS asserted) and a valid /J/K set of code-groups (SSD) is not received. If this condition is detected, then the LU3X34FT will assert RXER and present RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B codegroups until at least two IDLE code groups are detected. In addition, the false carrier counter (address 13h) will be incremented by one. Once at least two IDLE code-groups are detected, RXER and CRS become deasserted. Far-End Fault Indication. Autonegotiation provides a mechanism for transferring information from the local station to the link partner that a remote fault has occurred for 100Base-TX. As autonegotiation is not currently specified for operation over fiber, the far-end fault indication function (FEFI) provides this capability for 100Base-FX applications. A remote fault is an error in the link that one station can detect while the other cannot. An example of this is a disconnected wire at a station's transmitter. This station will be receiving valid data and detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other station. A 100Base-FX station that detects such a remote fault may modify its transmitted IDLE stream from all ones to a group of 84 ones followed by a single 0. This is referred to as the FEFI IDLE pattern. The FEFI function is controlled by bit 11 of register 18h. It is initialized to 1 (enabled) if the FOSEL pin is at logic high level during powerup or reset. If the FEFI function is enabled the LU3X34FT will HALT all current operations and transmit the FEFI IDLE pattern when FOSD signal is deasserted following a good link indication from the link integrity monitor. FOSD signal is generated internally from the FORX circuit. Transmission of the FEFI IDLE pattern will continue until FORX signal is asserted. If three or more FEFI IDLE patterns are detected by the LU3X34FT, then bit 4 of the basic mode status register (address 01h) is set to one until read by management. Additionally, upon detection of Lucent Technologies Inc.
10Base-T Module
The 10Base-T transceiver module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link integrity functions, as defined in the standard. Figure 4 provides an overview for the 10Base-T module. The LU3X34FT 10Base-T module is comprised of the following functional blocks:
s s s s s s s
Manchester encoder and decoder Collision detector Link test function Transmit driver and receiver Serial and parallel interface Jabber & SQE test functions Polarity detection and correction
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Functional Description (continued)
RXCLK CRS TPRX RECEIVE FILTER FILTER SMART SQUELCH CLOCK RECOVERY 10BASE-T RECEIVE PCS RXDV RXD[3:0] COL 10M PHY LOOPBACK PATH TXEN TPTX 10/100 TRANSMIT DRIVER WAVE SHAPER 10BASE-T TRANSMIT PCS TXER TXD[3:0] TXCLK
5-7910(F)
Figure 4. 10Base-T Module Data Path Operation Modes The LU3X34FT 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-duplex mode the LU3X34FT functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL pin signals squelch jabber, and the CRS is asserted during transmit and receive. In full-duplex mode the LU3X34FT can simultaneously transmit and receive data. Manchester Encoder/Decoder. Data encoding and transmission begins when the transmit enable input (TXEN) goes high and continues as long as the transceiver is in good link state. Transmission ends when the transmit enable input goes low. The last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0. Decoding is accomplished by a differential input receiver circuit and a phase-locked loop that separates the Manchester-encoded data stream into clock signals and NRZ data. The decoder detects the end of a frame when no more midbit transitions are detected. Within one and a half bit times after the last bit, carrier sense is deasserted. Transmit Driver and Receiver. LU3X34FT integrates all the required signal conditioning functions in its 10Base-T block such that external filters are not required. Only an isolation transformer and impedance matching resistors are needed for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated properly. Smart Squelch. The smart squelch circuit is responsible for determining when valid data is present on the differential receive. The LU3X34FT implements an intelligent receive squelch on the TPRX differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs. The signal at the start of the packet is checked by the analog squelch circuit and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally, the signal must exceed the original squelch level within a further 150 ns to ensure that the input waveform will not be rejected. Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present.
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Link Test Function. A link pulse is used to check the integrity of the connection with the remote end. If valid link pulses are not received, the link detector disables the 10Base-T twisted-pair transmitter, receiver, and collision detection functions. The link pulse generator produces pulses as defined in the IEEE 802.3 10Base-T standard. Each link pulse is nominally 100 ns in duration and is transmitted every 16 ms, in the absence of transmit data. Automatic Link Polarity Detection. The LU3X34FT's 10Base-T transceiver module incorporates an automatic link polarity detection circuit. The inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive receive packets are received with inverted end-of-packet pulses. If the input polarity is reversed, the error condition will be automatically corrected and reported in bit 15 of register 1Ch. The automatic link polarity detection function can be disabled by setting bit 3 of register 1Ah.
Functional Description (continued)
Valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end of packet. Once good data has been detected the squelch levels are reduced to minimize the effect of noise causing premature end of packet detection. The receive squelch threshold level can be lowered for use in longer cable applications. This is achieved by setting bit 11 of register address 1Ah. Carrier Sense. Carrier sense (CRS) may be asserted due to receive activity once valid data is detected via the smart squelch function. For 10 Mbits/s half-duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mbits/s full-duplex operation, the CRS is asserted only due to receive activity. CRS is deasserted following an end of packet. Collision Detection. For half-duplex operation, a 10Base-T collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. If the ENDEC is transmitting when a collision is detected. The COL signal remains set for the duration of the collision. SQE Test Function. Approximately 1 s after the transmission of each packet, a signal quality error (SQE) signal of approximately 10-bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. This function can be disabled by setting bit 12 of register 1Ah. The SQE test function is disabled in full-duplex mode. Jabber Function. The jabber function monitors the LU3X34FT's output and disables the transmitter if it attempts to transmit a longer than legal-sized packet. If TXEN is high for greater than 24 ms, the 10Base-T transmitter will be disabled and COL will go active-high. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted. This signal has to be deasserted for approximately 256 ms (the unjab time) before the jabber function re-enables the transmit outputs and deasserts COL signal. The jabber function can be disabled by setting bit 10 of register 1Ah.
Clock Synthesizer
The LU3X34FT implements a clock synthesizer that generates all the reference clocks needed from a single external frequency source. The clock source must be a TTL level signal at 25 MHz 50 ppm.
Autonegotiation
The autonegotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast link pulse (FLP) bursts provide the signaling used to communicate autonegotiation abilities between two devices at each end of a link segment. For further detail regarding autonegotiation, refer to clause 28 of the IEEE 802.3u specification. The LU3X34FT supports four different Ethernet protocols, so the inclusion of autonegotiation ensures that the highest performance protocol will be selected based on the ability of the link partner. The autonegotiation function within the LU3X34FT can be controlled either by internal register access or by the use of configuration pins. At powerup and at device reset, the configuration pins are sampled. If disabled, autonegotiation will not occur until software enables bit 12 in register 0. If autonegotiation is enabled, the negotiation process will commence immediately.
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Advance Data Sheet June 1999
The autonegotiation link partner ability register at address 5h indicates the abilities of the link partner as indicated by autonegotiation communication. The contents of this register are considered valid when the autonegotiation complete bit (bit 5, register address 01h) is set.
Functional Description (continued)
When autonegotiation is enabled, the LU3X34FT transmits the abilities programmed into the autonegotiation advertisement register at address 04h via FLP bursts. Any combination of 10 Mbits/s, 100 Mbits/s, halfduplex, and full-duplex modes may be selected. Autonegotiation controls the exchange of configuration information. Upon successful autonegotiation, the abilities reported by the link partner are stored in the autonegotiation link partner ability register at address 05h. The contents of the autonegotiation link partner ability register are used to automatically configure to the highest performance protocol between the local and far-end nodes. Software can determine which mode has been configured by autonegotiation by comparing the contents of register 04h and 05h and then selecting the technology whose bit is set in both registers of highest priority relative to the following list. 1. 100Base-TX full duplex (highest priority) 2. 100Base-TX half duplex 3. 10Base-T full duplex 4. 10Base-T half duplex (lowest priority) The basic mode control register at address 00h provides control of enabling, disabling, and restarting of the autonegotiation function. When autonegotiation is disabled, the speed selection bit (bit 13) controls switching between 10 Mbits/s or 100 Mbits/s operation, while the duplex mode bit (bit 8) controls switching between full-duplex operation and half-duplex operation. The speed selection and duplex mode bits have no effect on the mode of operation when the autonegotiation enable bit (bit 12) is set. The basic mode status register at address 01h indicates the set of available abilities for technology types (bits 15 to 11), autonegotiation ability (bit 3), and extended register capability (bit 0). These bits are hardwired to indicate the full functionality of the LU3X34FT. The BMSR also provides status on the following: 1. Whether autonegotiation is complete (bit 5). 2. Whether the link partner is advertising that a remote fault has occurred (bit 4). 3. Whether a valid link has been established (bit 2). The autonegotiation advertisement register at address 04h indicates the autonegotiation abilities to be advertised by the LU3X34FT. All available abilities are transmitted by default, but any ability can be suppressed by writing to this register or configuring external pins.
Reset Operation
The LU3X34FT can be reset either by hardware or software. A hardware reset is accomplished by applying a negative pulse, with a duration of at least 1 ms, to the RSTZ pin of the LU3X34FT during normal operation. A software reset is activated by setting the RESET bit in the basic mode control register (bit 15, register 00h). This bit is self-clearing and, when set, will return a value of 1 until the software reset operation has completed. Hardware reset operation samples the pins and initializes all registers to their default values. This process includes re-evaluation of all hardware configurable registers. A hardware reset affects all four PHYs in the device. A software reset can reset an individual PHY. It latches all configuration pins dedicated to the corresponding PHY but does not latch the external pins common to all four PHYs. Logic levels on several I/O pins are detected during the hardware and software reset period to determine the initial functionality of LU3X34FT. Some of these pins are used as output ports after reset operation. Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated configuration pins can be tied to Vcc or ground directly. Configuration pins multiplexed with logic level output functions should be either weakly pulled-up or weakly pulled-down through resistors. Configuration pins multiplexed with LED outputs should be set up with one of the following circuits shown in Figure 5.
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description (continued)
I/O PIN
VCC
10 k
10 k
I/O PIN
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
5-7911(F)
Figure 5. Hardware RESET Configurations PHY Address The PHY device address is stored in bits [4:0] of the PHY address register (register address 19h). The upper 3 bits of this field are initialized by the three I/O pins designated as PHY[4:2] during powerup or hardware reset and can be changed afterward by writing into this register address (19h). The lower 2 bits are initialized to the port number of the PHY. These unique 5-bit addresses are used during serial management interface communication. LED Configuration The LU3X34FT provides four LED output pins for each of its four ports. In addition to the default functions associated with their pin names, there are several registers that allow users to customize LED operations. Register 11h (programmable LED register) at PHY address 2 implement even more flexible LED configurations. Via the programmable LED register, each of the LEDs may be configured to operate in one the following modes: link, speed, duplex, receive, transmit, solid when link is up and blinks during activity, remote fault, and collision. Bits [0:3] in these registers allow the user to invert the on/off logic for each of these four programmable LEDs individually. Note that all LED circuits are switched under the control of the programmable LED register whenever the content of register 11h differs from its default value. Register 17h implements more LED configuration funcitons. With these registers, unused LED can be individually turned off to reduce power consumption. Fiber Mode Select A logic 1 level on pin 151, 157, 48, or 54 sets each channel in fiber mode individually. These pins are latched during reset operation. Pin 54 sets channel 3, pin 48 sets channel 2, pin 157 sets channel 1, and pin 151 sets channel 0 of the quad. Autonegotiation and Speed Configuration The four sets of five pins listed in Table 9 configure the speed capability of each channel of LU3X34FT. The logic state of these pins, at powerup or reset, are latched into the advertisement register (register address 04h) for autonegotiation purpose. These pins are also used for evaluating the default value in the base mode control register (register 00h) according to the following table.
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Functional Description (continued)
Table 9. Initial Values for Autonegotiation Registers Configuration Pins at RESET ANEN Pin 51[3] Pin 45[2] Pin 154[1] Pin 148[0] 0 0 0 0 0 1 100FD Pin 61[3] Pin 89[2] Pin 110[1] Pin 135[0] (bit 4.8) 1 0 0 0 0 X 100HD Pin 53[3] Pin 47[2] Pin156[1] Pin 150[0] (bit 4.7) X 1 1 0 0 X 10FD Pin 40 [3] Pin 121[2] Pin 122[1] Pin1[0] (bit 4.6) X 1 0 1 0 X 10HD Pin 52[3] Pin 46[2] Pin 155[1] Pin 149[0] (bit 4.5) X X X X 1 X Registers Initial Value
AUTONEG reg 0.12
SPEED reg 0.13
DUPLEX reg 0.8
0 0 0 0 0 1
1 1 1 0 0 0
1 1 0 1 0 0
100Base-X PCS Configuration The logic state of BPSCR, BP4B5B, and BPALIGN can be attained through bit configuration.
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers
The LU3X34FT has four independant PHYs in it. Each PHY has its own identical set of registers as tabulated below. The PHY address differentiates which PHY to be read or written into. The following tables of registers are applicable to each register. Table 10. MII Management Registers Address 0h 1h 2h--3h 4h 5h 6h 7h--Fh 11h 13h 15h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh Register Name Control Register Status Register PHY Identifier Register Autonegotiation Advertisement Register Autonegotiation Link Partner Ability Register Autonegotiation Expansion Register IEEE Reserved Programmable LED False Carrier Counter Receive Error Counter PHY Control/Status Register Config 100 Register PHY Address Register Config 10 Register Status 100 Register Status 10 Register Interrupt Mask Register Interrupt Status Register Basic/Extended B B E E E E E E E E E E E E E E E E
Note: Legends: RO--Read only R/W--Read and write capable SC--Self-clearing LL--Latching low, unlatch on read LH--Latching high, unlatch on read COR--Clear on read
Table 11. Control Register (Register 0h) Bit(s) 15 Name Reset Description 1--PHY reset 0--Normal operation Setting this bit initiates the software reset function that resets the entire LU3X34FT device, except for the phase-locked loop circuit. It will relatch in autonegotiation configuration pin values (ANEN, FOSEL, 100FD, 100HD, 10FD, 10HD) and set all registers to their default values. The software reset process takes 25 s to complete. This bit, which is self-clearing, returns a value of 1 until the reset process is complete. R/W R/W SC Default 0h
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MII Registers (continued)
Table 11. Control Register (Register 0h) (continued) Bit(s) 14 Name Loopback Description 1--Enable loopback mode 0--Disable loopback mode This bit controls the PHY loopback operation that isolates the network transmitter outputs (TX) and routes the MII transmit data to the MII receive data path. This function should only be used when autonegotiation is disabled (bit 12 = 0). The specific PHY (10Base-T or 100Base-X) used for this operation is determined by bits 12 and 13 of this register. 1--100 Mbits/s 0--10 Mbits/s Link speed is selected by this bit or by autonegotiation if bit 12 of this register is set (in which case, the value of this bit is ignored). At powerup or reset, this bit will be set unless ANEN detects a logic 1 or both 100 FD and 100 HD pins detects logic 0 state. 1--Enable autonegotiation process 0--Disable autonegotiation process This bit determines whether the link speed should be set up by the autonegotiation process. It is set at powerup or hardware/ software reset, if the ANEN pin detects a logic 1 input level. 1--Powerdown 0--Normal operation Setting this bit puts the LU3X34FT into powerdown mode. During the powerdown mode, the MII interface are isolated and TXEN signal is ignored. The management interface remains active and can be used to reset this bit in order to exit the powerdown mode. 1--Isolate PHY from MII 0--Normal operation Setting this control bit isolates the part from the MII, with the exception of the serial management interface. When this bit is asserted, the LU3X34FT does not respond to TXD[3:0], TXEN, and TXER inputs, and it presents a high impedance on its TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS outputs. This bit is initialized to the logic level of ISOLATE pin at powerup or hard reset. Value of this bit also follows the ISOLATE pin transition. R/W R/W Default 0h
13
Speed Selection
R/W
Pin
12
Autonegotiation Enable
R/W
Pin
11
Powerdown
R/W
0h
10
Isolate
R/W
Pin
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 11. Control Register (Register 0h) (continued) Bit(s) 9 Name Restart Autonegotiation Description R/W Default 0h
8
7
6:0
R/W, SC 1--Restart autonegotiation process 0--Normal operation Setting this bit while autonegotiation is enabled forces a new autonegotiation process to start. This bit is self-clearing and returns to 0 after the autonegotiation process has commenced. R/W Duplex Mode 1--Full-duplex mode 0--Half-duplex mode If autonegotiation is disabled, this bit determines the duplex mode for the link. At powerup or reset, this bit is set to 1 only if ANEN pin detects a logic 0 and either 100FD or 10FD pin detects a logic 1. R/W Collision Test (only applica- 1--Enable COL signal test ble while in PHY loopback 0--Disable COL signal test mode) When set, this bit will cause the COL signal of MII interface to be asserted in response to the assertion of TXEN Reserved Not used. RO
Pin
0h
0h
Table 12. Status Register Bit Definitions (Register 1h) Bit(s) 15 Name 100Base-T4 Description 1--Capable of 100Base-T4 0--Not capable of 100Base-T4 This bit is hardwired to 0, indicating that the LU3X34FT does not support 100Base-T4. 1--Capable of 100Base-X full-duplex mode 0--Not capable of 100Base-X full-duplex mode This bit is hardwired to 1, indicating that the LU3X34FT supports 100Base-X fullduplex mode. 1--Capable of 100Base-X half-duplex mode 0--Not capable of 100Base-X half-duplex mode This bit is hardwired to 1, indicating that the LU3X34FT supports 100Base-X halfduplex mode. 1--Capable of 10 Mbits/s full-duplex mode 0--Not capable of 10 Mbits/s full-duplex mode This bit is hardwired to 1, indicating that the LU3X34FT supports 10Base-T fullduplex mode. R/W RO Default 0h
14
100Base-X Full Duplex
RO
1h
13
100Base-X Half Duplex
RO
1h
12
10 Mbits/s Full Duplex
RO
1h
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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MII Registers (continued)
Table 12. Status Register Bit Definitions (Register 1h) (continued) Bit(s) 11 Name 10 Mbits/s Half Duplex Description R/W RO Default 1h
10
9:7 6
5
4
3
1--Capable of 10 Mbits/s half-duplex mode 0--Not capable of 10 Mbits/s half-duplex mode This bit is hardwired to 1, indicating that the LU3X34FT supports 10Base-T halfduplex mode. 100Base-T2 1--Capable of 100Base-T2 0--Not capable of 100Base-T2 This bit is hardwired to 0, indicating that the LU3X34FT does not support 100Base-T2. Reserved Ignore when read. MF Preamble Suppression 1--Accepts management frames with preamble suppressed 0--Will not accept management frames with preamble suppressed This bit is hardwired to 1, indicating that the LU3X34FT accepts management frame without preamble. A minimum of 32 preamble bits are required following power-on or hardware reset. One IDLE bit is required between any two management transactions as per IEEE 802.3u specification. Autonegotiation Complete 1--Autonegotiation process completed 0--Autonegotiation process not completed If autonegotiation is enabled, this bit indicates whether the autonegotiation process has been completed. Remote Fault 1--Remote fault detected 0--Remote fault not detected This bit is latched to 1 if the RF bit in the autonegotiation link partner ability register (bit 13, register 05h) is set or the receive channel meets the far-end fault indication function criteria. It is unlatched when this register is read. Autonegotiation Ability 1--Capable of autonegotiation 0--Not capable of autonegotiation This bit defaults to 1, indicating that LU3X34FT is capable of autonegotiation.
RO
0h
RO RO
0h 1h
RO
0h
RO, LH
0h
RO
1h
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 12. Status Register Bit Definitions (Register 1h) (continued) Bit(s) 2 Name Link Status Description 1--Link is up 0--Link is down This bit reflects the current state of the link-test-fail state machine. Loss of a valid link causes a 0 latched into this bit. It remains 0 until this register is read by the serial management interface. 1--Jabber condition detected 0--Jabber condition not detected During 10Base-T operation, this bit indicates the occurrence of a jabber condition. It is implemented with a latching function so that it becomes set until it is cleared by a read. 1--Extended register set 0--No extended register set This bit defaults to 1, indicating that the LU3X34FT implements extended registers. R/W RO, LL Default 0h
1
Jabber Detect
RO, LH
0h
0
Extended Capability
RO
1h
Table 13. PHY Identifier (Register 2h) Bit(s) 15:0 Name PHY-ID[15:0] Description R/W RO Default 0043h
IEEE Address
Table 14. PHY Identifier (Register 3h) Bit(s) 15:10 Name PHY-ID[15:0] Description R/W RO Default 7440h
IEEE Address/ Model No./ Rev. No.
Table 15. Advertisement (Register 4h) Bit(s) 15 Name Next Page Description 1--Capable of next page function 0--Not capable of next page function This bit is defaults to 0, indicating that LU3X34FT is not next page capable. Reserved. 1--Remote fault has been detected 0--No remote Fault has been detected This bit is written by serial management interface for the purpose of communicating the remote fault condition to the autonegotiation link partner. These 2 bits default to 0. R/W RO Default 0h
14 13
Reserved Remote Fault
RO R/W
0h 0h
12:11
IEEE Reserved
R/W
0h
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MII Registers (continued)
Table 15. Advertisement (Register 4h) (continued) Bit(s) 10 Name Flow Control Description 1--MAC sublayer is capable of pausebased flow control 0--MAC sublayer not capable of pausebased flow control This bit advertises the MAC sublayer has pause/flow control capability of operation when set in full-duplex mode. This must be set only when the PHY is advertising 10FD/100FD modes. At hardware reset, this bit is set to 1 if the PAUSE pin detects logic 1. This bit defaults to 0, indicating that the LU3X34FT does not support 100BaseT4. This 4-bit field contains the advertised ability of this PHY. At powerup or reset, the logic level of 100FD, 100HD, 10FD, and 10HD pins are latched into bits 8 through 5, respectively. These 5 bits are hardwired to 00001h, indicating that the LU3X34FT supports IEEE 802.3 CSMA/CD. R/W R/W Default Pin
9
Technology Ability Field for 100Base-T4 Technology Ability Field
RO
0h
8:5
R/W
Pin
4:0
Selector Field
R/W
01h
Table 16. Autonegotiation Link Partner Ability (Register 5h) Bit(s) 15 14 Name Next Page Acknowledge Description 1--Capable of next page function 0--Not capable of next page function 1--Link partner acknowledges reception of the ability data word 0--Not acknowledged 1--Remote fault has been detected 0--No remote fault has been detected Supported technologies. Encoding definitions. R/W RO RO Default 0h 0h
13 12:5 4:0
Remote Fault Technology Ability Field Selector Field
RO RO RO
0h 0h 0h
Table 17. Autonegotiation Expansion Register (Register 6h) Bit(s) 15:5 4 Name Reserved Parallel Detection Fault Description Reserved. 1--Fault has been detected 0--No fault detected This bit is set if the parallel detection fault state of the autonegotiation arbitration state machine is visited during the autonegotiation process. It will remain set until this register is read. R/W RO RO, LH Default 0h 0h
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 17. Autonegotiation Expansion Register (Register 6h) (continued) Bit(s) 3 Name Description R/W RO Default 0h
2
1
0
Link Partner Next Page Capa- 1--Link partner is next page capable ble 0--Link partner is not next page capable This bit indicates whether the link partner is next page capable. It is meaningful only when the autonegotiation complete bit (bit 5, register 1) is set. Next Page Capable 1--Local device is next page capable 0--Local device is not next page capable This bit defaults to 0, indicating that LU3X34FT is not next page capable. Page Received 1--A new page has been received 0--No new page has been received This bit is latched to 1 when a new link code word page has been received. This bit is automatically cleared when the autonegotiation link partner ability register (register 05h) is read by management interface. Link Partner Autonegotiable 1--Link partner is autonegotiable 0--Link partner is not autonegotiable
RO
0h
RO, LH
0h
RO
0h
Table 18. Programmable LED (Register 11h) Only Under PHY Address for Port 2 Bit(s) 15:13 Name Function of LEDACT Pin Description Programable LED output with the following settings: [000]: link [001]: speed [010]: duplex [011]: receive [100]: transmit [101]: solid when link is up, blinks during activity [110]: remote fault [111]: collision Programable LED output with the following settings: [000]: link [001]: speed [010]: duplex [011]: receive [100]: transmit [101]: solid when link is up, blinks during activity [110]: remote fault [111]: collision R/W R/W Default 100
12:10
Function of LEDFD Pin
R/W
010
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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MII Registers (continued)
Table 18. Programmable LED [Register 11h] Only Under PHY Address for Port 2 (continued) Bit(s) 9:7 Name Function of LED100 Pin Description Programable LED output with the following settings: [000]: link [001]: speed [010]: duplex [011]: receive [100]: transmit [101]: solid when link is up, blinks during activity [110]: remote fault [111]: collision Programable LED output with the following settings: [000]: link [001]: speed [010]: duplex [011]: receive [100]: transmit [101]: solid when link is up, blinks during activity [110]: remote fault [111]: collision Each bit controls the inversion option for one LED. If set to 1, LED is OFF when the programmed activity is true and ON when the programmed activity is false. Listed below are the relationship between the control bits and LED. bit 3: link LED bit 2: activity LED bit 1: full-duplex LED bit 0: speed 100 LED R/W R/W Default 001
4:6
Function of LEDLNK Pin
R/W
000
3:0
LED Inversion Modes
R/W
0000
Table 19. False Carrier Counter (Register 13h) Bit(s) 15:0 Name False Carrier Count Description Number of false carrier conditions since reset or read. The counter is incremented once for each packet that has false carrier condition detected. This counter may roll over depending on value of CSMODE bit (bit 13 of register 17h). R/W RO, COR Default 0h
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 20. Receive Error Counter (Register 15h) Bit(s) 15:0 Name RX Error Count Description Number of receive errors since last reset. The counter is incremented once for each packet that has receive error condition detected. This counter may roll over depending on value of the CSMODE bit (bit 13 of register 17h). R/W RO, COR Default 0h
Table 21. PHY Control/Status Register (Register 17h) Bit(s) 15 14 Name Reserved FOSEL Description R/W RO RO Default 0h Pin
13
12
11
10
9
Reserved. 1--Fiber mode 0--TX mode For 100Base-X operation, this bit determines whether LU3X34FT interfaces with the network through the internal 100Base-TX transceiver or using external fiber-optic transceiver. It is initialized to the logic level of FOSEL pin at powerup, hardware, or software reset. CSMODE 1--Counter sticks at FFFFh 0--Counters roll over This bit controls the operation of false carrier counter, and receive error counters. TPTXTR 1--Tri-state transmit pairs 0--Normal operation When this bit is set, the twisted-pair transmitter outputs af all four ports are tristated. Note that the twisted-pair transmit driver can be tri-stated by either this bit or the TPTXTR pin (pin 43). ThunderLAN Interrupt Enable 1--MDIO ThunderLAN interrupt enabled 0--MDIO ThunderLAN interrupt disabled This bit enables/disables the TI ThunderLAN interrupt mechanism. MF Preamble Suppression 1--MDIO preamble suppression enabled Enable 0--MDIO preamble suppression disabled LU3X34FT can accept management frames without preamble as described in bit 6 of register 1h. This bit allows the user to enable or disable the preamble suppression function. Speed Status 1--PHY is in 100 Mbits/s mode 0--PHY is in 10 Mbits/s mode This value is not defined during the autonegotiation period.
R/W
0h
R/W
0h
R/W
0h
R/W
1h
RO
0h
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MII Registers (continued)
Table 21. PHY Control/Status Register (Register 17h) (continued) Bit(s) 8 Name Duplex Status Description R/W RO Default 0h
7:6 5 4 3 2 1 0
1--PHY is in full-duplex mode 0--PHY is in half-duplex mode This value is not defined during the autonegotiation period. Reserved Reserved. LEDACT off 1--Tri-state LEDACT output 0--Normal operation LEDLNK off 1--Tri-state LEDLNK output 0--Normal operation (nonpulse stretched) Reserved Reserved. LEDFD off 1--Tri-state LEDFD output 0--Normal operation LED100 off 1--Tri-state LED100 output 0--Normal operation (nonpulse stretched) LED Pulse Stretching Disable 1--LED pulse stretching disabled 0--LED pulse stretching enabled When set to 0 LEDFD and LEDACT outputs are stretched 48 ms--72 ms.
R/W R/W R/W R/W R/W R/W R/W
0h 0 0 0 0 0 0
Table 22. Config 100 Register (Register 18h) Bit(s) 15 14 13 12 11 Name BPSCR BP4B5B Reserved BPALIGN Enable FEFI Description 1--Disable scrambler/descrambler 0--Enable scrambler/descrambler 1--Disable 4B/5B encoder/decoder 0--Enable 4B/5B encoder/decoder Reserved. 1--Pass unaligned data to MII 0--Pass aligned data to MII 1--Enable FEFI 0--Disable FEFI This bit enables/disables far-end fault indicator function for 100Base-FX and 10Base-T operation. It is initialized to the logic level of FOSEL pins at powerup or reset. After reset, this bit is writable if and only if the FOSEL register (bit 14 of register 17h) is set. Reserved. 1--Force good link in 100 Mbits/s mode 0--Normal operation Reserved. 1--Passes HALT symbols to the MII 0--Normal operation R/W R/W R/W RO R/W R/W Default FOSEL 0h 0h 0h Pin
10 9 8:6 5
Reserved Force Good Link 100 Reserved Accept HALT
R/W R/W R/W R/W
1h 0h 01h 0h
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 22. Config 100 Register (Register 18h) (continued) Bit(s) 4 Name Load Seed Description R/W Default 0h
3
Burst Mode
2:0
Reserved
R/W, SC 1--Loads the scrambler seed 0--Normal operation Setting this bit loads the user seed stored in register 19h into the 100Base-X scrambler. The content of this bit returns to 0 after the loading process is completed and no transmit is active. R/W 1--Burst mode 0--Normal operation Setting this bit expands the 722 s scrambler time-out period to 2,000 s. Reserved. RO
0h
0h
Table 23. PHY Address Register (Register 19h) Bit(s) 15:11 10:5 Name Reserved User Seed Description Reserved. User-modifiable seed data. When the load seed bit (bit 4 of register 18h) is set, bits 10 through 0 of this register are loaded into the 100Base-X scrambler. These 5 bits store the part address used by the serial management interface. Upper three of these bits are latched from the pins during pwerup or hard reset. Lower two bits are assigned automatically. R/W RO R/W Default 0h 21h
4:0
PHY Address
R/W
Pin
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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MII Registers (continued)
Table 24. Config 10 Register (Register 1Ah) Bit(s) 15 Name 10 Mbits/s Serial Mode Description 1--10 Mbits/s serial mode 0--10 Mbits/s nibble mode During 10Base-T operation, this bit determines whether the MII will be operating in nibble mode or serial mode. It is initialized to the logic level of SERSEL pin (pin 136). 1--Force 10 Mbits/s good link 0--Normal operation Reserved. 1--Signal quality error test enabled 0--Default SQE is disabled 1--Low squelch level selected 0--Normal squelch level selected 1--Jabber function disabled 0--Normal operation 1--Detect mode switching in 10 Mbit mode 0--Normal operation When set to 1, the part will restart autonegotiation when it is in 10 Mbit mode and detects 100 Mbit data reception. Reserved. 1--Disable digital filter 0--Normal operation Reserved. 1--Disable autopolarity function 0--Enable autopolarity function Reserved. R/W RO Default Pin
14 13 12 11 10 9
Force 10 Mbits/s Good Link Reserved SQE_EN Low Squelch Select Jabber Disable 100 Mbits/s Detect
R/W R/W R/W R/W R/W R/W
0h 0h 0h 0h 0h 0h
8 7 6:4 3 2:0
Reserved Digital Filter Disable Reserved Autopolarity Disable Reserved
RO R/W R/W R/W R/W
0h 0h 0h 0h 0h
Table 25. Status 100 Register (Register 1Bh) Bit(s) 15:14 13 12 11:0 Name Reserved PLL Lock Status False Carrier Status Reserved Description Reserved. 1--100 Mbits/s PLL locked 0--100 Mbits/s PLL not locked 1--False carrier detected 0--Normal operation Reserved. R/W RO RO RO, LH RO Default 0h 0h 0h 0h
Table 26. Status 10 Register (Register 1Ch) Bit(s) 15 14:0 Name Polarity Reserved Description 1--Polarity of cable is swapped 0--Polarity of cables is correct Reserved. R/W RO RO Default 0h 0h
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 27. Interrupt Mask Register (Register 1Dh) Bit(s) 15 14 13 12 11 10 9 8 7 6:0 Name False Carrier Status Description R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO Default 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h
0--Enable interrupt 1--Disable interrupt Receiver Error Counter 0--Enable interrupt Full 1--Disable interrupt Reserved Reserved. Remote Fault 0--Enable interrupt 1--Disable interrupt Autonegotiation Com- 0--Enable interrupt plete 1--Disable interrupt Link Up 0--Enable interrupt 1--Disable interrupt Link Down 0--Enable interrupt 1--Disable interrupt Data Recovery 100 Lock 0--Enable interrupt Up 1--Disable interrupt Data Recovery Lock 0--Enable interrupt Down 1--Disable interrupt Reserved Reserved.
Table 28. Interrupt Status Register (Register 1Eh) Bit(s) 15 Name False Carrier Counter Full Description R/W RO, LH Default 0h
14
13 12 11 10 9 8 7 6:0
1--False carrier counter has rolled over 0--False carrier counter has not rolled over Receiver Error Counter 1--Receive error counter has rolled over Full 0--Receive error counter has not rolled over Reserved Reserved. Remote Fault 1--Remote fault observed by PHY 0--Remote fault not observed by PHY Autonegotiation Com- 1--Autonegotiation has completed plete 0--Autonegotiation has not completed Link Up 1--Link is up 0--No change on link status Link Down 1--Link has gone down 0--No change on link status Data Recovery 100 Lock 1--Data recovery has locked Up 0--Data recovery is not locked Data Recovery 100 Lock 1--Data recovery is not locked Down 0--Data recovery has locked Reserved Reserved.
RO, LH
0h
RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH RO
0h 0h 0h 0h 0h 0h 0h 0h
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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dc and ac Specifications
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 29. Absolute Maximum Ratings Parameter Ambient Operating Temperature Storage Temperature Voltage on Any Pin with Respect to Ground Maximum Supply Voltage Table 30. Operating Conditions Parameter Operating Supply Voltage Power Dissipation: 100 Mbits/s TX with LEDs 100 Mbits/s FX with LEDs 10 Mbits/s with LEDs Autonegotiating with LEDs Symbol -- PD PD PD PD Min 3.135 -- -- -- -- Typ* 3.3 -- -- -- -- Max 3.46 480 450 480 200 Unit V mA mA mA mA Symbol TA Tstg -- -- Min 0 -65 -0.5 -- Max 70 150 5 5 Unit C C V V
* Typical power dissipations are specified at 3.3 V and 25 C. This is the power dissipated by the LU3X34FT.
Table 31. dc Characteristics Symbol VDD VSS IDD IDD IDD IDD VIH VIL VOH VOL IOLL IOHL IOLM Parameter Recommended Power Supply Supply Current 100Base-TX Supply Current 10Base-TX Supply Current Autonegotiation Mode Supply Current 100Base-FX TTL Input High Voltage TTL Input Low Voltage TTL Output High Voltage TTL Output Low Voltage Output Low Current LED Pins Output High Current LED Pins Output Low Current MII Pins Conditions -- VDD = 3.3 V, VSS = 0.0 V full-duplex traffic VDD = 3.3 V, VSS = 0.0 V full-duplex traffic VDD = 3.3 V, VSS = 0.0 V no link VDD = 3.3 V, VSS = 0.0 V full-duplex traffic VDD = 3.3 V, VSS = 0.0 V VDD = 3.3 V, VSS = 0.0 V VDD = 3.3 V, VSS = 0.0 V VDD = 3.3 V, VSS = 0.0 V -- -- -- Min 3.0 0.0 -- -- -- -- 2.0 -- 2.4 -- -- -- -- Max 3.6 0.0 480 480 200 450 -- 0.8 -- 0.4 10 10 4 Unit V V mA mA mA mA V V V V mA mA mA
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
dc and ac Specifications (continued)
Table 31. dc Characteristics (continued) Symbol IOHM VIH VIL VOH VOL MII CIN Parameter Output High Current MII Pins PECL Input High Voltage PECL Input Low Voltage PECL Output High Voltage PECL Output Low Voltage Input Capacitance Conditions -- -- -- -- -- -- Min -- Max 4 Unit mA V V V V pF
VDD - 1.16 VDD - 0.88 VDD - 1.81 VDD - 1.47 VDD - 1.02 -- -- VDD - 1.62 -- 8
Clock Timing
Table 32. Clock Timing Symbol t1 t2 t3 Parameter Clock High Pulse Width Clock Low Pulse Width Clock Period* Min 17 17 40 Max 23 23 40 Unit ns ns ns
* Specified at 50 ppm.
t1 CLK_25
t2
t3
5-7912(F).r1
Figure 6. Clock Timing
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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Clock Timing (continued)
Table 33. Transmit Clock (Input and Output) Symbol t1 Parameter TXCLK High Pulse Width (100 Mbits/s) TXCLK High Pulse Width (10 Mbits/s MII) TXCLK High Pulse Width (10 Mbits/s serial) Xin Rise to TXCLK Rise (100 Mbits/s) Xin Rise to TXCLK Rise (10 Mbits/s MII) Xin Rise to TXCLK Rise (10 Mbits/s serial) TXCLK Low Pulse Width (100 Mbits/s) TXCLK Low Pulse Width (10 Mbits/s MII) TXCLK Low Pulse Width (10 Mbits/s serial) TXCLK Period (100 Mbits/s)* TXCLK Period (10 Mbits/s MII)* TXCLK Period (10 Mbits/s serial)* Min 14 140 35 -- -- -- 14 140 35 40 400 100 Max 26 260 65 -- -- -- 26 260 65 40 400 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns
t2
t3
t4
* Specified at 100 ppm. t1 TXCLK t2 t3 t4
XIN
5-7913(F)
Figure 7. Transmit Clock (Input and Output)
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Clock Timing (continued)
Table 34. Management Clock Symbol t1 t2 t3 t4 Parameter MDC Low Pulse Width MDC High Pulse Width MDC Period MDIO(I) Setup to MDC Rising Edge Min 200 200 400 10 Max -- -- -- -- Unit ns ns ns ns
t1 MDC t4 MDIO(I)
t2
t3
t5
t6 MDIO(O)
5-7914(F)
Figure 8. Management Clock
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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Clock Timing (continued)
Table 35. MII Receive Timing Symbol t1 t2 t3 Parameter RXER, RXDV, RXD[3:0] Setup to RXCLK Rise RXER, RXDV, RXD[3:0] Hold After RXCLK Rise RXCLK High Pulse Width (100 Mbits/s) RXCLK High Pulse Width (10 Mbits/s MII) RXCLK High Pulse Width (10 Mbits/s serial) RXCLK Low Pulse Width (100 Mbits/s) RXCLK Low Pulse Width (10 Mbits/s MII) RXCLK Low Pulse Width (10 Mbits/s serial) RXCLK Period (100 Mbits/s) RXCLK Period (10 Mbits/s MII) RXCLK Period (10 Mbits/s serial) Min 10 10 14 200 50 14 140 35 40 400 100 Max -- -- 26 200 50 26 260 65 40 400 100 Unit ns ns ns ns ns ns ns ns ns ns ns
t4
t5
t5 t3 RXCLK t4 t1 t2
RXER, RXDV, RXD[3:0]
5-7915(F).r1
Figure 9. MII Receive Timing
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Clock Timing (continued)
Table 36. MII Transmit Timing Symbol t1 t2 Parameter TXER, TXEN, TXD[3:0] Setup to TXCLK Rise TXER, TXEN, TXD[3:0] Delay After TXCLK Rise Min 10 0 Max -- 25 Unit ns ns
t1 TXCLK
t2
TXER, TXEN, TXD[3:0]
DATA
DATA
5-7916(F)
Figure 10. MII Transmit Timing
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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Clock Timing (continued)
Table 37. Transmit Timing Symbol t1 t2 t3 t4 Parameter TXEN Sampled to CRS High (100 Mbits/s) TXEN Sampled to CRS High (10 Mbits/s) TXEN Sampled to CRS Low (100 Mbits/s) TXEN Sampled to CRS Low (10 Mbits/s) Transmit Latency (100 Mbits/s) Transmit Latency (10 Mbits/s) Sampled TXEN Inactive to End of Frame (100 Mbits/s) Sampled TXEN Inactive to End of Frame (10 Mbits/s) Min 0 -- 0 -- 6 4 -- -- Max 4 1.5 16 16 14 -- 17 5 Unit bits bits bits bits bits bits bits bits
TXCLK
TXEN t1 CRS t3 TPTX PREAMBLE
5-7917(F)
t2
t4
Figure 11. Transmit Timing
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Clock Timing (continued)
Table 38. Receive Timing Symbol t1 Parameter Receive Frame to Sampled Edge of RXDV (100 Mbits/s) Receive Frame to Sampled Edge of RXDV (10 Mbits/s) Receive Frame to CRS High (100 Mbits/s) Receive Frame to CRS High (10 Mbits/s) End of Receive Frame to Sampled Edge of RXDV (100 Mbits/s) End Receive Frame to Sampled Edge of RXDV (10 Mbits/s) End of Receive Frame to CRS Low (100 Mbits/s) End of Receive Frame to CRS Low (10 Mbits/s) Min -- -- -- -- -- -- 13 -- Max 15 22 13 5 12 4 24 4.5 Unit bits bits bits bits bits bits bits bits
t2 t3
t4
RXCLK t1 RXDV t2 CRS t3 t4 TPRX DATA
5-7918(F)
Figure 12. Receive Timing
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
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Clock Timing (continued)
Table 39. Reset and Configuration Timing Symbol t1 t2 t3 t4 Parameter Power on to Reset High Reset Pulse Width Configuration Pin Setup Configuration Pin Hold Min 0.5 0.5 0.5 0.5 Max -- -- -- -- Unit ms ms ms ms
VCC t1 RSTZ t3 CONFIG
5-7919(F)
t2
t4
Figure 13. Reset and Configuration Timing
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LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Clock Timing (continued)
Table 40. PMD Characteristics Symbol t1 t2 t3 t4 t5 t6 Parameter TPTX+/TPTX- Rise Time TPTX+/TPTX- Fall Time TP Skew FOTX+/FOTX- Rise Time FOTX+/FOTX- Fall Time FO Skew Min 3 3 0 -- -- -- Max 5 5 0.5 -- -- -- Unit ns ns ns ns ns ps
t1 t2 TPTX+ t3 TPTX- t4 t5 FOTX+ t6 FOTX-
5-7920(F)
Figure 14. PMD Characteristics
Lucent Technologies Inc.
45
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet June 1999
Clock Timing (continued)
VDD DIGITAL_VDD fb TX_VDD RX_VDD fb 1 CSVCC 4.7 F VDD 0.1 F 22 F
1:1 MAGNETICS TPTX+ 50 50 TPTX- TPRX+ 54 54 TPRX- 1000 pF 0.1 F 0.1 F 75 75 75 75
R145 TX+ TX- RX+ NC NC RX- NC NC
CHASSIS_GND R1 REF100 R2 REF10 TX_GND RX_GND DIGITAL_GND 680 pF--1000 pF 2 kV CHASSIS_GND
5-7510(F).r4
Figure 15. Connection Diagrams (10/100Base-TX Operation)
46
Lucent Technologies Inc.
Advance Data Sheet June 1999
LU3X34FT Quad 3 V 10/100 Ethernet Transceiver TX/FX
Outline Diagram
160-Pin PQFP 28 mm x 28 mm (measured in mm).
31.20 0.20 28.00 0.20 PIN #1 IDENTIFIER ZONE
160 121
1
120
28.00 0.20 31.20 0.20
40
81
41
80
DETAIL A
DETAIL B
3.42 0.25 4.07 MAX SEATING PLANE 0.10
0.65 TYP
0.25 MIN
1.60 REF
0.25 GAGE PLANE SEATING PLANE 0.73/1.03 DETAIL A DETAIL B 0.22/0.38
0.13/0.23
0.12
M
5-2132F).r13
Lucent Technologies Inc.
47
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved
June 1999 DS99-207LAN

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